1. Field of the Invention
The present invention relates to a semiconductor memory device which senses data read out from a memory cell by a sense amplifier to output the data.
2. Related Art
There is a known memory cell called an FBC (Floating Body Cell) which accumulates electric charges to a floating body of a transistor formed on an SOI (Silicon On Insulator) substrate. When “1” is written into the FBC, an SOI transistor performs a pentode operation, and holes generated by impact ionization are accumulated into the floating body. When “0” is written into the FBC, holes accumulated into the floating gate is discharged by setting a PN diode formed between a body and a drain to be forward bias. Consequently, when “0” is written into the FBC, a potential of the floating body becomes low, and a threshold voltage of the SOI transistor becomes high.
When the potential on the bit line is raised so much during a reading period, the SOI transistor performs pentode operation, and data of the memory cell holding “0” may be destroyed. Accordingly, the sense amplifier for performing read-out operation detects a current difference between “0” cell and “1” cell at a state of holding a bit line voltage to be a certain low voltage, by setting a word line to be a constant potential.
The FBC discriminates “1” and “0” depending on whether the number of the holes accumulated into the floating body in the SOI transistor is large or small. Because the bloating body is connected to outside via a PN junction part of the SOI transistor, the holes flow into from outside of the memory cell through a leak current in a reverse direction and a GIDL current. Therefore, data “0” may change into data “1”.
Furthermore, a charge pump phenomenon may occur to decrease holes. In the charge pump phenomenon, holes in the floating body are lost several pieces for each cycle of up/down of the word line voltage. Even in this case, data “1” may change into data “0”.
Under the above circumstances, The FBC needs a refresh operation in which a cell data is read out and written back while data stored in the memory cell does not change. The refresh operation is performed by the sense amplifier.
When data is read out from the FBC, a slight potential difference read out from the FBC has to be correctly sensed. However, the circuit configuration of the conventional sense amplifier may sense “1” as “0”, or “0” as “1” when performing high-speed operation (see T. Ohsawa et al., “An 18.5 ns 128 Mb SOI DRAM with a Floating Body Cell”, ISSCC Dig. Tech. Papers, pp458-459, February 2005).